`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:02:33 11/19/2020 
// Design Name: 
// Module Name:    PCreg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module PCreg(
    input [31:0] nPC,
	 input clk,
	 input reset,
	 input froze,
	 output reg[31:0] PC,
    output [31:0]PCadd4
    );
	
	always @(posedge clk)
	begin
		PC <= reset ? 32'h3000 : froze || nPC >= 32'h7000 ? PC : nPC;
	end
	
	assign PCadd4 = PC + 4;
	
endmodule
